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DDR3 SDRAM Supplier in Taiwan
Axeme - Hwaling Technology Co., Ltd. is proud to offer all of the leading brands in performance DDR3 SDRAM, at prices suitable for any budget. Most importantly, we back every one of our DDR3 SDRAM, DDR3 memory with the best one-on-one customer service you'll find anywhere. For over number years, we've offered the trusted DDR3 SDRAM, DDR3 memory to fit our customers requirement. If you have any questions about our DDR3 SDRAM, DDR3 memory, or to place an order, please call our sales department and speak with any one of our professional representatives for further information.
Item No. | Product Name | Density | Organization | Voltage | Package | File Download |
H2A401G1666A | DDR3 SDRAM | 1Gb | 64Mb x 16 | 1.5V | FBGA-96 | |
H2A401G1666B | DDR3 SDRAM | 1Gb | 64Mb x 16 | 1.5V | FBGA-96 | |
H2A401G1666O | DDR3 SDRAM | 1Gb | 64Mb x 16 | 1.5V | FBGA-96 | |
H2A401G0866B | DDR3 SDRAM | 1Gb | 128Mb x 8 | 1.5V | FBGA-78 | |
H2A402G1666A | DDR3 SDRAM | 2Gb | 128Mb x 16 | 1.5V | FBGA-96 | |
H2A402G1666B | DDR3 SDRAM | 2Gb | 128Mb x 16 | 1.5V | FBGA-96 | |
H2A402G1666C | DDR3 SDRAM | 2Gb | 128Mb x 16 | 1.5V | FBGA-96 | |
H2A402G1666O | DDR3 SDRAM | 2Gb | 128Mb x 16 | 1.5V | FBGA-96 | |
H2A402G1666P | DDR3 SDRAM | 2Gb | 128Mb x 16 | 1.5V | FBGA-96 | |
H2A402G1666Q | DDR3 SDRAM | 2Gb | 128Mb x 16 | 1.5V | FBGA-96 | |
H2A402G0866B | DDR3 SDRAM | 2Gb | 256Mb x 8 | 1.5V | FBGA-78 | |
H2A402G0866C | DDR3 SDRAM | 2Gb | 256Mb x 8 | 1.5V | FBGA-78 | |
H2A404G1666A | DDR3 SDRAM | 4Gb | 256Mb x 16 | 1.5V | FBGA-96 | |
H2A404G1666C | DDR3 SDRAM | 4Gb | 256Mb x 16 | 1.5V | FBGA-96 | |
H2A404G1666E | DDR3 SDRAM | 4Gb | 256Mb x 16 | 1.5V | FBGA-96 | |
H2A404G1666J | DDR3 SDRAM | 4Gb | 256Mb x 16 | 1.5V | FBGA-96 | |
H2A404G1666N | DDR3 SDRAM | 4Gb | 256Mb x 16 | 1.5V | FBGA-96 | |
H2A404G0866A | DDR3 SDRAM | 4Gb | 512Mb x 8 | 1.5V | FBGA-78 | |
H2A404G0866C | DDR3 SDRAM | 4Gb | 512Mb x 8 | 1.5V | FBGA-78 | |
H2A408G3266A | DDR3 SDRAM | 8Gb | 256Mb x 32 | 1.5V | FBGA-136 | |
H2A408G3286A | DDR3 SDRAM | 8Gb | 256Mb x 32 | 1.35V | FBGA-136 | |
H2A408G1666C | DDR3 SDRAM | 8Gb | 512Mb x 16 | 1.5V | FBGA-96 |
H2A401G1666A
1Gb (8Mx8Banksx16) DDR3 SDRAM
The H2A401G1666A is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1G bits which organized as 8Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ. Available package: FBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ. Available package: FBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
H2A401G1666B
1Gb (8Mx8Banksx16) DDR3 SDRAM
The H2A401G1666B is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1G bits which organized as 8Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ. Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ. Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
H2A401G1666O
1Gb (8Mx8Banksx16) DDR3 SDRAM
The H2A401G1666O is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1G bits which organized as 8Mbits x 8 banks by 16 bits.
This synchronous device achieves high speeddouble-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1,(3) On Die Termination (4) programmable driver strength data,(5) seamless BL4 access. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD andVDDQ. Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
This synchronous device achieves high speeddouble-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1,(3) On Die Termination (4) programmable driver strength data,(5) seamless BL4 access. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD andVDDQ. Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
H2A401G0866B
1Gb (16M×8Bank×8) DDR 3 SDRAM
The H2A401G0866B is a 1G bits DDR3 SDRAM, organized as 16,777,216 words × 8 banks × 8 bits. This device achieves high speed transfer rates up to 1600 Mb/sec/pin (DDR3-1600) for various applications.
The H2A401G0866B is designed to comply with the following key DDR3 SDRAM features such as posted /CAS, programmable /CAS Write Latency (CWL), ZQ calibration, on die termination and asynchronous reset. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous fashion.
The H2A401G0866B is designed to comply with the following key DDR3 SDRAM features such as posted /CAS, programmable /CAS Write Latency (CWL), ZQ calibration, on die termination and asynchronous reset. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous fashion.
H2A402G1666A
2Gb (16Mx8Banksx16) DDR3 SDRAM
The H2A402G1666A is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Available package: FBGA-96Ball (with 0.8mm x 0.8mm ball pitch)
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination,
- programmable driver strength data,
- seamless BL4 access with bank-grouping.
Available package: FBGA-96Ball (with 0.8mm x 0.8mm ball pitch)
H2A402G1666B
2Gb (16Mx8Banksx16) DDR3 SDRAM
The H2A402G1666B is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Available package: FBGA-96Ball (with 0.8mm x 0.8mm ball pitch)
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination,
- programmable driver strength data,
- seamless BL4 access with bank-grouping.
Available package: FBGA-96Ball (with 0.8mm x 0.8mm ball pitch)
H2A402G1666C
2Gb (16Mx8Banksx16) DDR3 SDRAM
The H2A402G1666C is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 2Gb DDR3 devices operates with a single power supply:1.5V±0.075V VDD and VDDQ.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination,
- programmable driver strength data,
- seamless BL4 access with bank-grouping.
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 2Gb DDR3 devices operates with a single power supply:1.5V±0.075V VDD and VDDQ.
H2A402G1666O
2Gb (16Mx8Banksx16) DDR3 SDRAM
The H2A402G1666O is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1G bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD andVDDQ. Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD andVDDQ. Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
H2A402G1666P
2Gb (16Mx8Banksx16) DDR3 SDRAM
The H2A402G1666P is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency
- write latency = read latency -1
- On Die Termination
- programmable driver strength data
- seamless BL4 access with bank-grouping
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
H2A402G1666Q
2Gb (16Mx8Banksx16) DDR3 SDRAM
The H2A402G1666Q is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1G bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 2Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD andVDDQ.
Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency
- write latency = read latency -1
- On Die Termination
- programmable driver strength data
- seamless BL4 access
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 2Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD andVDDQ.
Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)
H2A402G0866B
2Gb (32Mx8Banksx8) DDR3 SDRAM
The H2A402G0866B is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 32Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination,
- programmable driver strength data,
- seamless BL4 access with bank-grouping.
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)
H2A402G0866C
2Gb (32Mx8Banksx8) DDR3 SDRAM
The H2A402G0866C is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 32Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination,
- programmable driver strength data,
- seamless BL4 access with bank-grouping.
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)
H2A404G1666A
4Gb (32Mx8Banksx16) DDR3 SDRAM
The H2A404G1666A is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
H2A404G1666C
4Gb (32Mx8Banksx16) DDR3 SDRAM
The H2A404G1666C is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
H2A404G1666E
4Gb (32Mx8Banksx16) DDR3 SDRAM
The H2A404G1666E is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
H2A404G1666J
4Gb (32Mx8Banksx16) DDR3 SDRAM
The H2A404G1666J is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
H2A404G1666N
4Gb (32Mx8Banksx16) DDR3 SDRAM
The H2A404G1666N is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
H2A404G0866A
4Gb (64Mx8Banks×8) DDR3 SDRAM
The 4Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM Containing 4,294,967,296 bits. It is internally configured as an octal-bank DRAM.
The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.
The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.
H2A404G0866C
4Gb (64Mx8Banks×8) DDR3 SDRAM
The H2A404G0866C is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 4,294,967,296 bits which organized as 64Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 4Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination,
- programmable driver strength data,
- seamless BL4 access with bank-grouping.
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 4Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)
H2A408G3266A
8Gb (32Mx8Banks×32) DDR3 SDRAM
The H2A408G3266A is a high speed stack multi-chip package integrated 4Gbits x2 DDR3 SDRAM and fabricated with ultra high performance CMOS process containing 8G bits which organized as 32Mbits x 8 banks by 32 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ.
H2A408G3286A
8Gb (32Mx8Banks×32) DDR3 SDRAM
The H2A408G3286A is a high speed stack multi-chip package integrated 4Gbits x2 DDR3 SDRAM and fabricated with ultra high performance CMOS process containing 8G bits which organized as 32Mbits x 8 banks by 32 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.35V ±1.35V -0.065/+0.1V or 1.5V ± 0.075V VDD and VDDQ.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.35V ±1.35V -0.065/+0.1V or 1.5V ± 0.075V VDD and VDDQ.
H2A408G1666C
8Gb (64Mx8Banksx16) DDR3 SDRAM
The H2A408G1666C is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process which organized as 64Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination,
- programmable driver strength data,
- seamless BL4 access with bank-grouping.
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
With our advance research on day to day needs of consumer, our DDR3 SDRAM, DDR3 memory are at the front. We are best in the manufacturing of DDR3 SDRAM. Our strict inspections and testing have ensured that all our DDR3 SDRAM, DDR3 memory achieve a high level of performance even in harsh conditions. If you are looking for suppliers and long-term mutually beneficial partnership, we are ready to offer you our services.
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