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LPDDR4 SDRAM
Axeme - Hwaling Technology Co., Ltd. offers cutting-edge memory solutions with a focus on LPDDR4 SDRAM and LPDDR4X SDRAM technologies. Our LPDDR4 SDRAM delivers exceptional performance and low power consumption, making it ideal for mobile devices and high-performance computing applications. With our advanced low power SDRAM solutions, users can experience significant energy savings while maintaining high-speed data transfer rates. The LPDDR4X SDRAM, an enhancement of LPDDR4, provides even greater efficiency and performance, ensuring optimal operation in modern electronics. At Axeme - Hwaling Technology Co., Ltd., we are committed to delivering high-quality, reliable memory products that meet the demands of today's technology-driven world. Explore our comprehensive range of LPDDR4 SDRAM to find the perfect solution for your needs.
| Item No. | Product Name | Density | Organization | Voltage | Package | File Download |
| H2AB04G32D6C | LPDDR4 SDRAM | 4Gb | 128Mb x 32 | 1.8/ 1.1/ 1.1V | FBGA-200 | |
| H2AB08G32D6C | LPDDR4 SDRAM | 8Gb | 256Mb x 32 | 1.8/ 1.1/ 1.1V | FBGA-200 | |
| H2AB08G32E6R | LPDDR4 SDRAM | 8Gb | 256Mb x 32 | 1.8/ 1.1/ 1.1V | FBGA-200 | |
| H2AB16G32D6C | LPDDR4 SDRAM | 16Gb | 512Mb x 32 | 1.8/ 1.1/ 1.1V | FBGA-200 | |
| H2AB16G32E6R | LPDDR4 SDRAM | 16Gb | 512Mb x 32 | 1.8/ 1.1/ 1.1V | FBGA-200 | |
| H2AB32G32D6C | LPDDR4 SDRAM | 32Gb | 1024Mb x 32 | 1.8/ 1.1/ 1.1V | FBGA-200 | |
| H2AB32G32E6R | LPDDR4 SDRAM | 32Gb | 1024Mb x 32 | 1.8/ 1.1/ 1.1V | FBGA-200 | |
| H2AB32G64D6C | LPDDR4 SDRAM | 32Gb | 512Mb x 64 | 1.8/ 1.1/ 1.1V | FBGA-366 | |
| H2AB64G32E6R | LPDDR4 SDRAM | 64Gb | 2048Mb x 32 | 1.8/ 1.1/ 1.1V | FBGA-200 | |
| H2AB16G32E6C | LPDDR4X SDRAM | 16Gb | 512Mb x 32 | 1.8/ 1.1/ 0.6V | FBGA-200 |
H2AB04G32D6C
4Gb (16Mx8Banks×32) Low Power DDR4 SDRAM
H2AB04G32D6C uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation, our H2AB04G32D6C SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB04G32D6C effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB04G32D6C are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB04G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
For H2AB04G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB08G32D6C
8Gb (32Mx8Banks×32) Low Power DDR4 SDRAM
H2AB08G32D6C uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation, our H2AB08G32D6C SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB08G32D6C effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB08G32D6C are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB08G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
For H2AB08G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB08G32E6R
8Gb (32Mx8Banks×32) Low Power DDR4 SDRAM
H2AB08G32E6R uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation,our H2AB08G32E6R
SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB08G32E6R effectively consists
of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB08G32E6R are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB08G32E6R devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB08G32E6R effectively consists
of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB08G32E6R are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB08G32E6R devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB16G32D6C
16Gb (64Mx8Banks×32) Low Power DDR4 SDRAM
H2AB16G32D6C uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation, our H2AB16G32D6C SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB16G32D6C effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB16G32D6C are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB16G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
For H2AB16G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB16G32E6R
16Gb (64Mx8Banks×32) Low Power DDR4 SDRAM
H2AB16G32E6R uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation,our H2AB16G32E6R SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB16G32E6R effectively consists
of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB16G32E6R are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB16G32E6R devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB16G32E6R are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB16G32E6R devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB32G32D6C
32Gb (128Mx8Banks×32) Low Power DDR4 SDRAM
H2AB32G32D6C uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation,our H2AB32G32D6C SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB32G32D6C effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB32G32D6C are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB32G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
For H2AB32G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB32G32E6R
32Gb (128Mx8Banks×32) Low Power DDR4 SDRAM
H2AB32G32E6R uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation,our H2AB32G32E6R SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB32G32E6R effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB32G32E6R are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB32G32E6R devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
For H2AB32G32E6R devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB32G64D6C
32Gb (64Mx8Banks×64) Low Power DDR4 SDRAM
H2AB32G64D6C uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation, our H2AB32G64D6C SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB32G64D6C effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB32G64D6C are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a programmed sequence.
For H2AB32G64D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
and continue for a programmed number of locations in a programmed sequence.
For H2AB32G64D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB64G32E6R
64Gb (256Mx8Banks×32) Low Power DDR4 SDRAM
H2AB64G32E6R uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation,our H2AB64G32E6R SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the H2AB64G32E6R effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB64G32E6R are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
For H2AB64G32E6R devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
For H2AB64G32E6R devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2AB16G32E6C
16Gb (512Meg×32) Low Power DDR4 SDRAM
H2AB16G32E6C uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. Each command uses one clock cycle,during which command information is transferred on both the positive and negative edge of the clock. To achieve high-speed operation, our H2AB16G32E6C SDRAM adopt 16n-prefetch interface designed to transfer two data per clock cycle at the I/O pins.
A single read or write access for the H2AB16G32E6C effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB16G32E6C are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. For H2AB16G32E6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
A single read or write access for the H2AB16G32E6C effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB16G32E6C are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. For H2AB16G32E6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
Axeme - Hwaling Technology Co., Ltd. specializes in high-performance memory solutions, prominently featuring LPDDR4 SDRAM and LPDDR4X SDRAM. Our LPDDR4 SDRAM provides superior speed and efficiency, ideal for advanced mobile devices and computing applications. Leveraging low power SDRAM technology, our products are designed to deliver excellent performance while minimizing energy consumption, enhancing device battery life. The LPDDR4X SDRAM, an advanced version of LPDDR4, offers even lower power usage and higher data rates, making it perfect for cutting-edge electronics. Discover our range of LPDDR4 SDRAM solutions to achieve the ultimate balance of power and performance for your technological needs.
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