DDR4 SDRAM Manufacturer
16Gb (512Meg×32) Low Power DDR4 SDRAM
A single read or write access for the H2AB16G32E6C effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal SDRAM core and eight corresponding n-bit wide,one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the H2AB16G32E6C are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. For H2AB16G32E6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
- VDD1 = 1.70–1.95V; 1.80V nominal
- VDD2 = 1.06–1.17V; 1.10V nominal
- VDDQ = 0.57–0.65V; 0.60V nominal
- 1866MHz(data rate (per pin) range: 3733Mb/s)