DDR4 SDRAM Manufacturer
4Gb (16Mx8Banks×32) Low Power DDR4 SDRAM
For H2AB04G32D6C devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.