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DDR4 SDRAM Supplier in Taiwan
Axeme - Hwaling Technology Co., Ltd. designs best in class DDR4 SDRAM and provides manufacturing services for DDR4 memory with high engineering content. Keeping in mind the importance of clients' time, we make sure that our products are delivered to them within the promises time-period. Axeme - Hwaling Technology Co., Ltd.’s innovative technology and designs paralleled with our excellent customer service have propelled us to become one of the leading providers of DDR4 SDRAM, DDR4 memory today. We're always looking for intelligent, dedicated professionals with a passion for excellence to join us.
| Item No. | Product Name | Density | Organization | Voltage | Package | File Download |
| H2A904G08A6C | DDR4 SDRAM | 4Gb | 512Mb x 8 | 1.2V | FBGA-78 | |
| H2A904G08A6O | DDR4 SDRAM | 4Gb | 512Mb x 8 | 1.2V | FBGA-78 | |
| H2A904G16A6C | DDR4 SDRAM | 4Gb | 256Mb x 16 | 1.2V | FBGA-96 | |
| H2A908G08A6C | DDR4 SDRAM | 8Gb | 1024Mb x 8 | 1.2V | FBGA-78 | |
| H2A908G08A6O | DDR4 SDRAM | 8Gb | 1024Mb x 8 | 1.2V | FBGA-78 | |
| H2A908G16A6C | DDR4 SDRAM | 8Gb | 512Mb x 16 | 1.2V | FBGA-96 | |
| H2A908G16A6J | DDR4 SDRAM | 8Gb | 512Mb x 16 | 1.2V | FBGA-96 | |
| H2A916G16A6C | DDR4 SDRAM | 16Gb | 1024Mb x 16 | 1.2V | FBGA-96 |
H2A904G08A6C
4Gb (32Mx16Banks×8) DDR4 SDRAM
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 2 bank group with 4 banks for each bankgroup for x8 DRAM.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
H2A904G08A6O
4Gb (32Mx16Banks×8) DDR4 SDRAM
The 4Gb DDR4 SDRAM is organized as 32Mbit x8 I/Os x 16banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 2400Mb/sec/ pin (DDR4-2400) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V). The 4Gb DDR4 device is available in 78ball FBGAs.
The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V). The 4Gb DDR4 device is available in 78ball FBGAs.
H2A904G16A6C
4Gb (32Mx8Banks×16) DDR4 SDRAM
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
H2A908G08A6C
8Gb (64Mx16Banks×8) DDR4 SDRAM
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x8 DRAM.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
H2A908G08A6O
8Gb (64Mx16Banks×8) DDR4 SDRAM
The 8Gb DDR4 SDRAM is organized as 64Mbit x8 I/Os x 16banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 3200Mb/sec/ pin (DDR4-3200) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM fea-tures such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset. All of the control and address inputs are synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V). The 8Gb DDR4 device is available in 78ball FBGAs.
The chip is designed to comply with the following key DDR4 SDRAM fea-tures such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset. All of the control and address inputs are synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V). The 8Gb DDR4 device is available in 78ball FBGAs.
H2A908G16A6C
8Gb (64Mx8Banks×16) DDR4 SDRAM
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
H2A908G16A6J
8Gb (64Mx8Banks×16) DDR4 SDRAM
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
H2A916G16A6C
16Gb (128Mx8Banks×16) DDR4 SDRAM
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Axeme - Hwaling Technology Co., Ltd. is a national manufacturer and supplier that specialize in providing of DDR4 SDRAM, DDR4 memory related products. Our goal is to build a long-term relationship as your Product Name supplier by providing quality products and service that exceeds your expectations. With many years of experience, we have the core technical knowledge for DDR4 SDRAM to satisfy our customers' demands. With an extensive range available in stock and our fast, reliable service and support, Axeme - Hwaling Technology Co., Ltd. makes it easy for you to find and buy what you need.
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