H2A404G0866A

4Gb (64Mx8Banks×8) DDR3 SDRAM

The 4Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM Containing 4,294,967,296 bits. It is internally configured as an octal-bank DRAM.
The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.
Features
  • JEDEC Standard VDD/VDDQ = 1.5V±0.075V
  • 8 Internal memory banks (BA0-BA2)
  • Differential clock input (CK,/CK)
  • Bust length: 4 with Burst Chop (BC) and 8.
  • CAS Write Latency (CWL): 5, 6, 7, 8, 9
  • CAS Latency (CL): 6, 7, 8, 9, 10, 11, 12, 13
  • POSTED CAS ADDITIVE Programmable Additive
    Latency (AL): 0, CL-1, CL-2 clock
  • Programmable Sequential / Interleave Burst Type
  • 8n-bit prefetch architecture
  • Output Driver Impedance Control
  • Differential bidirectional data strobe
  • Internal(self) calibration:Internal self calibration
  • OCD Calibration
  • Dynamic ODT (Rtt_Nom & Rtt_WR)
  • Auto Self-Refresh
  • Self-Refresh Temperature
  • RoHS compliance and Halogen free
  • Packages: 78-Balls BGA for x8 components