4Gb (32Mx8Banksx16) DDR3 SDRAM

The H2A404G1666N is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.

The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
  • JEDEC Standard VDD/VDDQ = +1.5V ± 0.075V
  • Operating temperature:
    • Normal operating temperature: TC = 0~85°C
    • Extended temperature: TC = 85~95°C
  • Supports JEDEC clock jitter specification
  • Fully synchronous operation
  • Fast clock rate: 800/933MHz
  • Differential Clock, CK & CK#
  • Bidirectional differential data strobe –DQS & DQS#.
  • 8 internal banks for concurrent operation
  • 8n-bit prefetch architecture
  • Pipelined internal architecture
  • Precharge & active power down
  • Programmable Mode & Extended Mode registers
  • Additive Latency (AL): 0, CL-1, CL-2
  • Programmable Burst lengths: 4, 8
  • Burst type: Sequential / Interleave
  • Output Driver Impedance Control
  • Write Leveling
  • ZQ Calibration
  • RoHS compliant
  • Auto Refresh and Self Refresh
  • 8,192 Refresh Cycles / 64ms
  • Average Refresh Period
    • 7.8us @ 0°C ≦TC≦ +85°C
    • 3.9us at 85°C < Tcase ≦ 95°C
  • 96-ball 7.5 x 13.5 x 1.2mm FBGA package
    • Pb and Halogen Free