H2A408G1666C
8Gb (64Mx8Banksx16) DDR3 SDRAM
The H2A408G1666C is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process which organized as 64Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination,
- programmable driver strength data,
- seamless BL4 access with bank-grouping.
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
Features
- Power Supply: VDD = VDDQ = 1.5V ±0.075V
- All inputs and outputs are compatible with SSTL_15 interface.
- Fully differential clock inputs (CK, /CK) operation.
- Eight Banks
- Posted CAS by programmable additive latency
- Bust length: 4 with Burst Chop (BC) and 8.
- CAS Write Latency (CWL): 5,6,7,8
- CAS Latency (CL): 6, 7, 8, 9, 10, 11
- Write Latency (WL) =Read Latency (RL) -1.
- Bi-directional Differential Data Strobe (DQS).
- Data inputs on DQS centers when write.
- Data outputs on DQS, /DQS edges when read.
- On chip DLL align DQ, DQS and /DQS transition with CK transition.
- DM mask write data-in at the both rising and falling edges of the data strobe.
- Sequential & Interleaved Burst type available both for 8 & 4 with BC.
- Multi Purpose Register (MPR) for pre-defined pattern read out
- On Die Termination (ODT) options: Synchronous ODT, Dynamic ODT, and Asynchronous ODT
- Auto Refresh and Self Refresh
- 8,192 Refresh Cycles / 64ms
- Refresh Interval: 85°C ~ 95°C
- RoHS Compliance
- Driver Strength: RZQ/7, RZQ/6(RZQ=240Ω)
- High Temperature Self-Refresh rate enable
- ZQ calibration for DQ drive and ODT
- RESET pin for initialization and reset function
