Axeme - Hwaling Technology Co., Ltd.

Hwaling Technology is based in Taipei, Taiwan. As the interaction of Communication, Electronic Consumer and Computing gadgets has became the main stream in consumer lives. Hwaling practices his specialty with long-term experience in this memory field to drive quality products and services to customers.

DDR4 SDRAM

Axeme - Hwaling Technology Co., Ltd.’s professional knowledge and advanced equipment enables us to achieve low cost, efficiency and quality control, which in turn result in superior products and competitive pricing. Our company has been specializing in DRAM IC and DDR4 SDRAM for many years.
Item No. Product Name Density Organization Voltage Package Remark File Download
H2A904G08A6C DDR4 SDRAM 4Gb 512Mb x 8 1.2V FBGA-78 7.5x11mm H2A904G08A6C _DDR4_32Mx16 (2.4 MB)
H2A904G16A6C DDR4 SDRAM 4Gb 256Mb x 16 1.2V FBGA-96 7.5x13.5mm H2A904G16A6C _DDR4_32Mx8 (2.3 MB)
H2A908G08A6C DDR4 SDRAM 8Gb 1024Mb x 8 1.2V FBGA-78 7.5x11mm H2A908G08A6C _DDR4_64Mx16 (2.4 MB)
H2A908G16A6C DDR4 SDRAM 8Gb 512Mb x 16 1.2V FBGA-96 7.5x13mm H2A908G16A6C_DDR4_64Mx8B (2.5 MB)
H2A908G16A6J DDR4 SDRAM 8Gb 512Mb x 16 1.2V FBGA-96 7.5x13mm H2A908G16A6J _DDR4_64Mx8B (1.4 MB)
H2A916G16A6C DDR4 SDRAM 16Gb 1024Mb x 16 1.2V FBGA-96 10x13mm H2A916G16A6C _DDR4_128Mx8 (2.5 MB)

H2A904G08A6C

4Gb (32Mx16Banks×8) DDR4 SDRAM

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 2 bank group with 4 banks for each bankgroup for x8 DRAM.

The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

H2A904G16A6C

4Gb (32Mx8Banks×16) DDR4 SDRAM

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.

The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

H2A908G08A6C

8Gb (64Mx16Banks×8) DDR4 SDRAM

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x8 DRAM.

The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

H2A908G16A6C

8Gb (64Mx8Banks×16) DDR4 SDRAM

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.

The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

H2A908G16A6J

8Gb (64Mx8Banks×16) DDR4 SDRAM

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.

The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

H2A916G16A6C

16Gb (128Mx8Banks×16) DDR4 SDRAM

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.

The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
The DDR4 SDRAM is specifically designed to meet our customers’ most demanding needs, as its service-friendly design provides reliable performance and easy maintenance. Please contact our sales office in Taiwan to discuss the suitability of DDR4 SDRAM for your applications or email us for more information.