H2A908G08A6O
8Gb (64Mx16Banks×8) DDR4 SDRAM
The 8Gb DDR4 SDRAM is organized as 64Mbit x8 I/Os x 16banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 3200Mb/sec/ pin (DDR4-3200) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM fea-tures such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset. All of the control and address inputs are synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V). The 8Gb DDR4 device is available in 78ball FBGAs.
The chip is designed to comply with the following key DDR4 SDRAM fea-tures such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset. All of the control and address inputs are synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V). The 8Gb DDR4 device is available in 78ball FBGAs.
Features
- JEDEC standard 1.2V (1.14V~1.26V)
- VDDQ = 1.2V (1.14V~1.26V)
- 8-bit pre-fetch
- 16 internal banks (x8): 4 groups of 4 banks each
- Programmable CAS Latency (posted CAS): 10,11,12,13,14,15,16,17,18,19,20,22,24
- Programmable Additive Latency: 0, CL-2 or CL-1 clock
- Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
- Bi-directional Differential Data-Strobe
- Internal (self) calibration: calibration through ZQ pin (RZQ: 240 ohm ± 1%)
- On Die Termination using ODT pin
- Connectivity Test Mode (TEN) is Supported
- Asynchronous Reset
- CRC for Read/Write data security
- Command address parity check
- DBI (Data Bus Inversion)
- Gear down mode
- POD (Pseudo Open Drain) interface for data input/output
- Internal VREF for data inputs
- External VPP for DRAM Activating Power
- PPR and sPPR is supported
