The 8Gb DDR4 SDRAM is organized as 64Mbit x8 I/Os x 16banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 3200Mb/sec/ pin (DDR4-3200) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM fea-tures such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset. All of the control and address inputs are synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V). The 8Gb DDR4 device is available in 78ball FBGAs.