H2A916G16A6C
16Gb (128Mx8Banks×16) DDR4 SDRAM
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks,2 bank group with 4 banks for each bankgroup for x16 DRAM.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Features
- VDD = VDDQ = 1.2V ±60mV
- VPP = 2.5V, –125mV, +250mV
- On-die, internal, adjustable VREFDQ generation
- 8 internal banks (x16): 2 groups of 4 banks each
- 8n-bit prefetch architecture
- Command/Address latency (CAL)
- Multipurpose register READ and WRITE capability
- Write and read leveling
- Self refresh mode
- Low-power auto self refresh (LPASR)
- Temperature controlled refresh (TCR)
- Fine granularity refresh
- Self refresh abort
- Maximum power saving
- Output driver calibration
- Nominal, park, and dynamic on-die termination
- Data bus inversion (DBI) for data bus
- Command/Address (CA) parity
- Databus write cyclic redundancy check (CRC)
- Per-DRAM addressability
- JEDEC JESD-79-4 compliant
- sPPR and hPPR capability
