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64Mb (512K×4Banks×32) Synchronous DRAM
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The H2A164M3233N is Synchronous Dynamic Random Access Memory (SDRAM) organized as 512K words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.