128Mb (1M×4Banks×32) Synchronous DRAM

The H2A11283233B is Synchronous Dynamic Random Access Memory (SDRAM) organized as 1Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
  • 1,048,576 Words × 4 banks × 32 bits organization
  • Single 3.3V±0.3V Power Supply
  • Self Refresh Mode
  • CAS Latency: 2 and 3
  • Burst Length: 1, 2, 4, 8 and full page
  • Burst Read, Single Writes Mode
  • Byte Data Controlled by DQM
  • Auto-precharge and Controlled Precharge
  • 4K Refresh cycles / 64 mS
  • Interface: LVTTL
  • Packaged in TSOP II 86 pin, 400 mil – 0.50
  • Using Lead free materials with RoHS compliant