Description

The H2A302G1656C is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 2G bits which organized as 16Mbits x 8 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features:

1. posted CAS with additive latency
2. write latency = read latency -1
3. Off-Chip Driver (OCD) impedance adjustment and On Die Termination
4. normal and weak strength data output driver.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.