H2A408G3286A
8Gb (32Mx8Banks×32) DDR3 SDRAM
The H2A408G3286A is a high speed stack multi-chip package integrated 4Gbits x2 DDR3 SDRAM and fabricated with ultra high performance CMOS process containing 8G bits which organized as 32Mbits x 8 banks by 32 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.35V ±1.35V -0.065/+0.1V or 1.5V ± 0.075V VDD and VDDQ.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination
- programmable driver strength data,
- seamless BL4 access.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.35V ±1.35V -0.065/+0.1V or 1.5V ± 0.075V VDD and VDDQ.
Features
- VDD/VDDQ = 1.35V -0.065/+0.1V.
- Backward compatible to VDD = VDDQ = 1.5V ±0.075V.Supports DDR3 devices to be backward compatible in 1.5V applications.
- Fully differential clock inputs (CK, /CK) operation.
- Eight Banks
- Posted CAS by programmable additive latency
- Bust length: 4 with Burst Chop (BC) and 8.
- CAS Write Latency (CWL): 5,6,7,8
- CAS Latency(CL): 5,6,7,8,9,10,11
- Write Latency (WL) =Read Latency (RL) -1.
- Bi-directional Differential Data Strobe (DQS).
- Data inputs on DQS centers when write.
- Data outputs on DQS, /DQS edges when read.
- On chip DLL align DQ, DQS and /DQS transition with CK transition.
- DM mask write data-in at the both rising and falling edges of the data strobe.
- Sequential & Interleaved Burst type available both for 8 & 4 with BC.
- Multi Purpose Register (MPR) for pre-defined pattern read out
- On Die Termination (ODT)options: Synchronous ODT, Dynamic ODT, and Asynchronous ODT
- Auto Refresh and Self Refresh
- 8,192 Refresh Cycles / 64ms
- Refresh Interval:7.8us Tcasebetween 0°C ~ 85°C
- RoHS Compliance
- Driver Strength:RZQ/7, RZQ/6(RZQ=240Ω)
- High Temperature Self-Refresh rate enable
- ZQ calibration for DQ drive and ODT
- RESET pin for initialization and reset function