H2A401G0866B
1Gb (16M×8Bank×8) DDR 3 SDRAM
The H2A401G0866B is a 1G bits DDR3 SDRAM, organized as 16,777,216 words × 8 banks × 8 bits. This device achieves high speed transfer rates up to 1600 Mb/sec/pin (DDR3-1600) for various applications.
The H2A401G0866B is designed to comply with the following key DDR3 SDRAM features such as posted /CAS, programmable /CAS Write Latency (CWL), ZQ calibration, on die termination and asynchronous reset. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous fashion.
The H2A401G0866B is designed to comply with the following key DDR3 SDRAM features such as posted /CAS, programmable /CAS Write Latency (CWL), ZQ calibration, on die termination and asynchronous reset. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous fashion.
Features
- JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
- Double Data Rate architecture: two data transfers per clock cycle
- Eight internal banks for concurrent operation
- 8 bit prefetch architecture
- CAS Latency: 6, 7, 8, 9, 10 and 11 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)
- Programmable read burst ordering: interleaved or nibble sequential
- Bi-directional, differential data strobes (DQS and /DQS) are transmitted / received with data
- Edge-aligned with read data and center-aligned with write data
- DLL aligns DQ and DQS transitions with clock
- Differential clock inputs (CK and /CK) Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate)
- Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiency
- Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
- Auto-precharge operation for read and write bursts
- Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
- Precharged Power Down and Active Power Down
- Data masks (DM) for write data
- Programmable CAS Write Latency (CWL) per operating frequency
- Write Latency WL = AL + CWL
- Interface: SSTL_15
- Packaged in WBGA 78 Ball (8x10.5 mm2 ), using lead free materials with RoHS compliant
