The H2A35120856B is a 512M bits DDR2 SDRAM, organized as 16,777,216 words x 4 banks x 8 bits.
This device achieves high speed transfer rates up to 800Mb/sec/pin (DDR2-800) for general applications. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CLK rising and /CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- /DQS pair in a source synchronous fashion.