Product Name : 4Gb (32Mx8Banksx16) DDR3 SDRAM

Item No. : H2A404G1666J


The H2A404G1666J is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
H2A404G1666J_DDR3_256Mx16 (836 KB)
  • VDD = VDDQ = 1.5V ± 0.075V (JEDEC Standard Power Supply).
  • 8 Internal memory banks (BA0-BA2).
  • Differential clock input (CK,/CK).
  • Programmable /CAS Latency: 6, 7, 8, 9, 10, 11, 12, 13
  • /CAS WRITE Latency (CWL): 5, 6, 7, 8, 9
  • POSTED CAS ADDITIVE Programmable Additive
    Latency (AL): 0, CL-1, CL-2 clock
  • Programmable Sequential / Interleave Burst Type.
  • Programmable Burst Length: 4, 8.
    Through ZQ pin (RZQ:240 ohm±1%)
  • 8n-bit prefetch architecture.
  • Output Driver Impedance Control.
  • Differential bidirectional data strobe.
  • Internal(self) calibration: Internal self calibration.
  • OCD Calibration.
  • Dynamic ODT (Rtt_Nom & Rtt_WR)
  • Auto Self-Refresh
  • Self-Refresh Temperature
  • RoHS compliance and Halogen free
  • Packages: 96-Ball BGA for x16 components