The H2A408G3266A is a high speed stack multi-chip package integrated 4Gbits x2 DDR3 SDRAM and fabricated with ultra high performance CMOS process containing 8G bits which organized as 32Mbits x 8 banks by 32 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
posted CAS with additive latency,
write latency = read latency -1,
On Die Termination
programmable driver strength data,
seamless BL4 access.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ.