The H2A31281656B is a 128M bits DDR2 SDRAM, organized as 2,097,152words x 4 banks x 16 bits. The -25 grade parts are compliant to the DDR2 800 (6-6-6) specification . The -3 grade parts is compliant to the DDR2-667 (5-5-5) specification.
JEDEC specifications require the refresh rate to double when TCASE exceeds +85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when TCASE is < 0°C or > +85°C. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source synchronous fashion.