H2A302G0856B
2Gb (32Mx8Banks×8) DDR2 SDRAM
The H2A302G0856B is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 2G bits which organized as 32Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features:
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR2 devices operate with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-60Ball.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- Off-Chip Driver (OCD) impedance adjustment and On Die Termination
- normal and weak strength data output driver.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR2 devices operate with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-60Ball.
Features
- JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
- All inputs and outputs are compatible with SSTL_18 interface.
- Fullydifferential clock inputs (CK, /CK) operation.
- EightBanks
- Posted CAS
- Bust length: 4 and 8.
- Programmable CAS Latency (CL): 5, 6
- Programmable Additive Latency (AL):0, 1, 2, 3, 4, 5
- Write Latency (WL) =Read Latency (RL) -1.
- Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL)
- Bi-directional DifferentialData Strobe (DQS).
- Data inputs on DQS centers when write.
- Data outputs on DQS, /DQS edges when read.
- On chip DLL align DQ, DQS and /DQS transition with CK transition.
- DM mask write data-in at the both rising and falling edges of the data strobe.
- Sequential & Interleaved Burst type available.
- Off-Chip Driver (OCD) Impedance Adjustment
- On Die Termination (ODT)
- Auto Refresh and Self Refresh
- 8,192 Refresh Cycles / 64ms
- RoHS Compliance
- Partial Array Self-Refresh (PASR)
- High Temperature Self-Refresh rate enable
