H2A801G32B6B
1Gb (4Mx8Banks×32) Low Power DDR3 SDRAM
This LPDDR3 is a high-speed SDRAM device internally configured as an 8-Bank memory and contains 1,073,741,824 bits.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
Features
- VDD1 = 1.7~1.95V
- VDD2/ VDDCA/ VDDQ = 1.14V~1.30V
- Data width: x32
- Clock rate: up to 1066 MHz
- Data rate: up to 2133 Mbps
- 8 internal banks for concurrent operation
- 8n pre-fetch operation
- Burst length: 8
- Per Bank Refresh
- Partial Array Self-Refresh (PASR)
- On-die termination (ODT)
- Deep Power Down Mode (DPD Mode)
- Double data rate architecture
- Clock Stop capability
- Programmable Read and Write Latencies (RL/WL)
- Bidirectional differential data strobe
- VFBGA178 (11mm x 11.5mm)
