H2A725632B6B
256Mb (2Mx4Banks×32) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as a 4-Bank memory. These devices contains 256Mb has 268,435,456 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
Features
- VDD1 = 1.7~1.95V
- VDD2/ VDDCA/ VDDQ = 1.14V~1.30V
- Data width: x32
- Clock rate: up to 533 MHz
- Data rate: up to 1066 Mbps
- Four-bit prefetch DDR architecture
- Four internal banks
- Programmable READ and WRITE latencies (RL/WL)
- Programmable burst lengths: 4, 8, or 16
- Auto refresh: All bank refresh mode only
- Partial Array Self-Refresh (PASR):
All bank or per bank, bank mask is supported but segment mask is not supported - Precharge command: All bank or per bank
- Read/ Write with auto-prechage
- Deep Power Down Mode (DPD Mode)
- Programmable output buffer driver strength
- Data mask (DM) for write data
- Clock Stop capability during idle periods
- Double data rate for data output
- Differential clock inputs
- Bidirectional differential data strobe
- Interface: HSUL_12
- JEDEC LPDDR2-S4B compliance
- Support package:
Single channel: VFBGA 134 ball (10mm x11.5mm)
