H2A908G16A6O
8Gb (62Mx8Banks×16) DDR4 SDRAM
The 8Gb DDR4 SDRAM is organized as 64Mbit x16 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 3200Mb/sec/ pin (DDR4-3200) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V)VDDQ and 2.5V(2.375V~2.75V)VPP. The 8Gb DDR4 device is available in 96ball FBGAs.
The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V)VDDQ and 2.5V(2.375V~2.75V)VPP. The 8Gb DDR4 device is available in 96ball FBGAs.
Features
- JEDEC standard 1.2V (1.14V~1.26V)
- VDDQ = 1.2V (1.14V~1.26V)
- VPP = 2.5V (2.375V~2.75V)
- 8-bit pre-fetch
- 8 Banks (2 Bank Groups)
- Programmable CAS Write Latency (CWL): 9, 10, 11, 12, 14, 16, 18, 20
- Programmable Additive Latency: 0, CL-2 or CL-1 clock
- Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
- Bi-directional Differential Data-Strobe
- Internal (self) calibration: calibration through ZQ pin (RZQ: 240 ohm ± 1%)
- On Die Termination using ODT pin
- Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C
- Support Industrial Temp (-40°C to 95°C)
- tREFI 7.8us at -40°C ≤ TCASE ≤ 85°C
- tREFI 3.9us at 85°C < TCASE ≤ 95°C
- Connectivity Test Mode (TEN) is Supported
- Asynchronous Reset
- CRC for Read/Write data security
- Command address parity check
- DBI (Data Bus Inversion)
- Gear down mode
- POD (Pseudo Open Drain) interface for data input/output
- Internal VREF for data inputs
- External VPP for DRAM Activating Power
- PPR and sPPR is supported
- All of Lead-Free products are compliant for RoHS
- All of products are Halogen-free
