H7A41G26D7CX is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 3 Vcc Power Supply, and with SPI interface.The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. Program operation allows the 2112-byte page writing in typical 300us and an erase operation can be performed in typical 2 ms on a 128K-byte block.
Data in the page can be read out at 10ns cycle time per word. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data.
An internal 4-bit ECC logic is implemented in the chip, which is enabled by default. The internal ECC can be disabled or enabled again by command. When the internal 4-bit ECC logic is disabled, the host side needs to handle the 4-bit ECC by host micro controller.
The serial peripheral interface (SPI) provides NAND Flash with a cost-effective non-volatile memory storage solution in systems where pin count must be kept to a minimum. It is also an alternative to SPI-NOR, offering superior write performance and cost per bit over SPI-NOR.
MEMORY CELL ARRAY
– (2K + 64) bytes x 64 pages x 1024 blocks
HARDWARE DATA PROTECTION
– Enable/Disable protection with WP# Pin
– Top or Bottom, Block selection combination
– Max cycling: 50K Program / Erase cycles
– Data retention: 10 Years (4bit/512byte ECC)
– Internal ECC can be enabled (4bit ECC)
– Block zero is a valid block and will be valid for at least 1K program-erase cycles with ECC