H7A2AG21C1CX
16G-Bit 3.3V NAND FLASH MEMORY
The H7A2AG21C1CX (16G-bit) NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#).
The H7A2AG21C1CX (16G-bit) NAND Flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe (DQS).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN).
The H7A2AG21C1CX (16G-bit) NAND Flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe (DQS).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN).
Features
- Open NAND Flash Interface (ONFI) 2.2-compliant1
- Multiple-level cell (MLC) technology
- Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Block size: 256 pages (1024K + 56K bytes)
– Plane size: 2 planes x 1024 blocks per plane
– Device size: 16Gb: 2048 blocks;32Gb: 4096 blocks - Synchronous I/O performance
– Up to synchronous timing mode 4
– Clock rate: 12ns (DDR)
– Read/write throughput per pin: 166 MT/s - Asynchronous I/O performance
– Up to asynchronous timing mode 5
– Read/write throughput per pin: 50 MT/s
– tRC/tWC: 20ns (MIN) - Array performance
– Read page: 75μs (MAX)
– Program page: 1300μs (TYP)
– Erase block: 3.8ms (TYP) - Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 2.7–3.6V - Command set: ONFI NAND Flash Protocol
- Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback - Operating temperature:
– Commercial: 0°C to +70°C - Package: 48-pin TSOP
