The H2A35121656I is a four bank DDR DRAM organized as 4 banks x 16Mbit x 8 . The H2A35121656I achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is designed to comply with the following key DDR2 SDRAM features:
posted CAS with additive latency,
write latency = read latency -1,
On Die Termination.
All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O s are synchronized with a pair of bidirectional strobes (DQS, DQS) in a source synchronous fashion.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.