The H2A32561656B is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features:
posted CAS with additive latency,
write latency = read latency -1,
Off-Chip Driver (OCD) impedance adjustment and On Die Termination
normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 256Mb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (8mmx12.5mm, 0.8mm x 0.8mm ball pitch).