H2A21281643B
128Mb (2Mx4Banks×16) DDR SDRAM
The H2A21281643B is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 134,217,728 bits which organized as 2Meg words x 4 banks by 16 bits.
The 128Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and It transfers the datafor both rising and falling edges of the system clock.It means the doubled data bandwidth can be achieved at the I/O pins.
Available packages:TSOPII 66P 400mil.
The 128Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and It transfers the datafor both rising and falling edges of the system clock.It means the doubled data bandwidth can be achieved at the I/O pins.
Available packages:TSOPII 66P 400mil.
Features
- 2.5V ± 0.2V Power Supply for DDR400/333
- Double Data Rate architecture; two data transfers per clock cycle
- Differential clock inputs (CLK and /CLK )
- DQS is edge-aligned with data for Read; center-aligned with data for Write
- CAS Latency: 2, 2.5 and 3
- Burst Length: 2, 4 and 8
- Auto Refresh and Self Refresh
- Precharged Power Down and Active Power Down
- Write Data Mask
- Write Latency = 1
- Maximum burst refresh cycle: 8
- Interface: SSTL_2
- Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
