The H2A264M1643B is CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM); organized as 1Meg words x 4 banks by 16 bits.
The 64Mb DDR SDRAM uses double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and it transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I/O pins.
Available packages: TSOPII 66P 400mil.