Axeme - Hwaling Technology Co., Ltd.

Hwaling Technology is based in Taipei, Taiwan. As the interaction of Communication, Electronic Consumer and Computing gadgets has became the main stream in consumer lives. Hwaling practices his specialty with long-term experience in this memory field to drive quality products and services to customers.

Quality DDR2/ DDR2 SDRAM Manufacturer

Axeme - Hwaling Technology Co., Ltd. is one of the leading manufacturers of DDR2/ DDR2 SDRAM and is highly regarded for its quality products.Our work is dedicated to the creation of progress with inspiring, innovative solutions and to a trusting partnership towards our customers and partners with common benefits. Innovative design, durability, high performance, and low maintenance requirement are the features of our DDR2/ DDR2 SDRAM. Also, our DDR2/ DDR2 SDRAM is illustrious in the market for its perfect designing, flawless performance, cost effectiveness, and other such features.
Item No. Product Name Density Organization Voltage Package File Download
H2A31281656B DDR2 SDRAM 128Mb 8Mb x 16 1.8V FBGA-84 H2A31281656B _DDR2_8Mx16(1.8 MB)
H2A32561656B DDR2 SDRAM 256Mb 16Mb x 16 1.8V FBGA-84 H2A32561656B_DDR2_16Mx16(1.8 MB)
H2A35121656B DDR2 SDRAM 512Mb 32Mb x 16 1.8V FBGA-84 H2A35121656B_DDR2_32Mx16(2.3 MB)
H2A35121656I DDR2 SDRAM 512Mb 32Mb x 16 1.8V FBGA-84 H2A35121656I_DDR2_32Mx16(1.8 MB)
H2A35120856B DDR2 SDRAM 512Mb 64Mb x 8 1.8V FBGA-60 H2A35120856B _DDR2_64Mx8(2.1 MB)
H2A301G1656B DDR2 SDRAM 1Gb 64Mb x 16 1.8V FBGA-84 H2A301G1656B_DDR2_64Mx16(878 KB)
H2A301G0856B DDR2 SDRAM 1Gb 128Mb x 8 1.8V FBGA-60 H2A301G0856B_DDR2_128Mx8(1.7 MB)
H2A302G1656B DDR2 SDRAM 2Gb 128Mb x 16 1.8V FBGA-84 H2A302G1656B_DDR2_128Mx16(1.9 MB)
H2A302G0856B DDR2 SDRAM 2Gb 256Mb x 8 1.8V FBGA-60 H2A302G0856B_DDR2_256Mx8(1.6 MB)

H2A31281656B

128Mb (2Mx4Banks×16) DDR2 SDRAM

The H2A31281656B is a 128M bits DDR2 SDRAM, organized as 2,097,152words x 4 banks x 16 bits. The -25 grade parts are compliant to the DDR2 800 (6-6-6) specification . The -3 grade parts is compliant to the DDR2-667 (5-5-5) specification.
JEDEC specifications require the refresh rate to double when TCASE exceeds +85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when TCASE is < 0°C or > +85°C. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source synchronous fashion.

H2A32561656B

256Mb (8Mx2Banks×16) DDR2 SDRAM

The H2A32561656B is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. Off-Chip Driver (OCD) impedance adjustment and On Die Termination
  4. normal and weak strength data output driver.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 256Mb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (8mmx12.5mm, 0.8mm x 0.8mm ball pitch).

H2A35121656B

512Mb (8Mx4Banks×16) DDR2 SDRAM

The H2A35121656B is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 8Mbits x 4 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. Off-Chip Driver (OCD) impedance adjustment and On Die Termination
  4. normal and weak strength data output driver.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 512 Mb DDR2 devices operate with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package:TFBGA-84Ball.

H2A35121656I

512Mb (8Mx4Banks×16) DDR2 SDRAM

The H2A35121656I is a four bank DDR DRAM organized as 4 banks x 16Mbit x 8 . The H2A35121656I achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is designed to comply with the following key DDR2 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination.

All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O s are synchronized with a pair of bidirectional strobes (DQS, DQS) in a source synchronous fashion.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.

H2A35120856B

1Gb (16Mx4Banksx8) DDR2 SDRAM

The H2A35120856B is a 512M bits DDR2 SDRAM, organized as 16,777,216 words x 4 banks x 8 bits.
This device achieves high speed transfer rates up to 800Mb/sec/pin (DDR2-800) for general applications. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CLK rising and /CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- /DQS pair in a source synchronous fashion.

H2A301G1656B

1Gb (8Mx8Banksx16) DDR2 SDRAM

The H2A301G1656B is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1,073,741,824 bits which organized as 8Mbits x 8 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. Off-Chip Driver (OCD) impedance adjustment and On Die Termination
  4. normal and weak strength data output driver.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ. Available package:
TFBGA-84Ball (with 0.8mm x 0.8mm ball pitch)

H2A301G0856B

1Gb (16Mx8Banks×8) DDR2 SDRAM

The H2A301G0856B is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1G bits which organized as 16Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin (DDR2-1066) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. Off-Chip Driver (OCD) impedance adjustment and On Die Termination
  4. normal and weak strength data output driver.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR2 devices operate with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-60Ball.

H2A302G1656B

2Gb (16Mx8Banks×16) DDR2 SDRAM

The H2A302G1656B is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 2G bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. Off-Chip Driver (OCD) impedance adjustment and On Die Termination
  4. normal and weak strength data output driver.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 2Gb DDR2 devices operate with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball.

H2A302G0856B

2Gb (32Mx8Banks×8) DDR2 SDRAM

The H2A302G0856B is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 2G bits which organized as 32Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. Off-Chip Driver (OCD) impedance adjustment and On Die Termination
  4. normal and weak strength data output driver.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR2 devices operate with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-60Ball.
At Axeme - Hwaling Technology Co., Ltd., we strive to bring you the best DDR2/ DDR2 SDRAM for the best price. We work hard to achieve quality at affordable prices for our customers through optimizing our entire value chain, by building long-term supplier relationships, investing in highly automated production and producing large volumes. In these 10 years, we have served generations of satisfied customers with our quality and values. If you are looking for DDR2/ DDR2 SDRAM, you are in the right place. At Axeme - Hwaling Technology Co., Ltd., you will find every kind of DDR2/ DDR2 SDRAM that you can think of, with something for all kind of business.