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LPDDR3 SDRAM
Axeme - Hwaling Technology Co., Ltd. is committed to developing LPDDR3 SDRAM that ultimately create innovative products that exceed customer expectations. We are the global leader in hardware & metal products. We develop, manufacture and distribute groundbreaking DRAM IC that shatter the status quo and help customers gain and maintain a competitive edge. We believe that our LPDDR3 SDRAM have very great potential for this type of development in hardware & metal products industry. Axeme - Hwaling Technology Co., Ltd. is committed to developing LPDDR3 SDRAM that ultimately create innovative products that exceed customer expectations.
| Item No. | Product Name | Density | Organization | Voltage | Package | File Download |
| H2A801G16B6B | LPDDR3 SDRAM | 1Gb | 64Mb x 16 | 1.8/ 1.2V | 178Ball | |
| H2A801G32B6B | LPDDR3 SDRAM | 1Gb | 32Mb x 32 | 1.8/ 1.2V | 178Ball | |
| H2A802G16B6B | LPDDR3 SDRAM | 2Gb | 128Mb x 16 | 1.8/ 1.2V | 178Ball | |
| H2A802G32B6B | LPDDR3 SDRAM | 2Gb | 64Mb x 32 | 1.8/ 1.2V | 178Ball | |
| H2A804G16B6B | LPDDR3 SDRAM | 4Gb | 256Mb x 16 | 1.8/ 1.2V | 178Ball | |
| H2A804G32B6B | LPDDR3 SDRAM | 4Gb | 128Mb x 32 | 1.8/ 1.2V | 178Ball |
H2A801G16B6B
1Gb (8Mx8Banks×16) Low Power DDR3 SDRAM
This LPDDR3 is a high-speed SDRAM device internally configured as an 8-Bank memory and contains 1,073,741,824 bits.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
H2A801G32B6B
1Gb (4Mx8Banks×32) Low Power DDR3 SDRAM
This LPDDR3 is a high-speed SDRAM device internally configured as an 8-Bank memory and contains 1,073,741,824 bits.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
H2A802G16B6B
2Gb (16Mx8Banks×16) Low Power DDR3 SDRAM
This LPDDR3 is a high-speed SDRAM device internally configured as an 8-Bank memory and contains 2,147,483,648 bits.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
H2A802G32B6B
2Gb (8Mx8Banks×32) Low Power DDR3 SDRAM
This LPDDR3 is a high-speed SDRAM device internally configured as an 8-Bank memory and contains 2,147,483,648 bits.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
H2A804G16B6B
4Gb (32Mx8Banks×16) Low Power DDR3 SDRAM
This LPDDR3 is a high-speed SDRAM device internally configured as an 8-Bank memory and contains 4,294,967,296 bits.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
H2A804G32B6B
4Gb (16Mx8Banks×32) Low Power DDR3 SDRAM
This LPDDR3 is a high-speed SDRAM device internally configured as an 8-Bank memory and contains 4,294,967,296 bits.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
This LPDDR3 device uses a double data rate architecture on the Command/ Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/ Row Buffer information.
Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
Axeme - Hwaling Technology Co., Ltd. requests you just to send your requirement and our technical team will get in touch to give you the best possible solution of LPDDR3 SDRAM. In addition, we receive immense support and reliance of our experienced professionals, who put their best in understanding and catering to the varied client needs. With the help of our professionals, we offer these products in various as per the varied requirements of our valuable clients. You can also visit Axeme - Hwaling Technology Co., Ltd.'s showroom where you can find excellent performance LPDDR3 SDRAM.
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