Home / Product Line
LPDDR2 SDRAM
Axeme - Hwaling Technology Co., Ltd. is committed to developing LPDDR2 SDRAM that ultimately create innovative products that exceed customer expectations. We are the global leader in hardware & metal products. We develop, manufacture and distribute groundbreaking DRAM IC that shatter the status quo and help customers gain and maintain a competitive edge. We believe that our LPDDR2 SDRAM have very great potential for this type of development in hardware & metal products industry. Axeme - Hwaling Technology Co., Ltd. is committed to developing LPDDR2 SDRAM that ultimately create innovative products that exceed customer expectations.
| Item No. | Product Name | Density | Organization | Voltage | Package | File Download |
| H2A725616B6B | LPDDR2 SDRAM | 256Mb | 16Mb x 16 | 1.8/ 1.2V | 134Ball | |
| H2A725632B6B | LPDDR2 SDRAM | 256Mb | 8Mb x 32 | 1.8/ 1.2V | 134Ball | |
| H2A751216B6B | LPDDR2 SDRAM | 512Mb | 32Mb x 16 | 1.8/ 1.2V | 134Ball | |
| H2A751232B6B | LPDDR2 SDRAM | 512Mb | 16Mb x 32 | 1.8/ 1.2V | 134Ball | |
| H2A701G16B6B | LPDDR2 SDRAM | 1Gb | 64Mb x 16 | 1.8/ 1.2V | 134Ball | |
| H2A701G32B6B | LPDDR2 SDRAM | 1Gb | 32Mb x 32 | 1.8/ 1.2V | 134Ball | |
| H2A702G16B6B | LPDDR2 SDRAM | 2Gb | 128Mb x 16 | 1.8/ 1.2V | 134Ball | |
| H2A702G32B6B | LPDDR2 SDRAM | 2Gb | 64Mb x 32 | 1.8/ 1.2V | 134Ball |
H2A725616B6B
256Mb (4Mx4Banks×16) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as a 4-Bank memory. These devices contains 256Mb has 268,435,456 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2A725632B6B
256Mb (2Mx4Banks×32) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as a 4-Bank memory. These devices contains 256Mb has 268,435,456 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2A751216B6B
512Mb (8Mx4Banks×16) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as a 4-Bank memory. These devices contains 512Mb has 536,870,912 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2A751232B6B
512Mb (4Mx4Banks×32) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as a 4-Bank memory. These devices contains 512Mb has 536,870,912 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2A701G16B6B
1Gb (16Mx4Banks×16) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as an 8-Bank memory. These devices contains 1 Gb has 1,073,741,824 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2A701G32B6B
1Gb (8Mx4Banks×32) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as an 8-Bank memory. These devices contains 1 Gb has 1,073,741,824 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2A702G16B6B
2Gb (32Mx4Banks×16) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as an 8-Bank memory. These devices contains 2 Gb has 2,147,483,648 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
H2A702G32B6B
2Gb (16Mx4Banks×32) Low Power DDR2 SDRAM
LPDDR2 is a high-speed SDRAM device internally configured as an 8-Bank memory. These devices contains 2 Gb has 2,147,483,648 bits.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.
For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
Axeme - Hwaling Technology Co., Ltd. requests you just to send your requirement and our technical team will get in touch to give you the best possible solution of LPDDR2 SDRAM. In addition, we receive immense support and reliance of our experienced professionals, who put their best in understanding and catering to the varied client needs. With the help of our professionals, we offer these products in various as per the varied requirements of our valuable clients. You can also visit Axeme - Hwaling Technology Co., Ltd.'s showroom where you can find excellent performance LPDDR2 SDRAM.
Related Product Categories