Axeme - Hwaling Technology Co., Ltd.

Hwaling Technology is based in Taipei, Taiwan. As the interaction of Communication, Electronic Consumer and Computing gadgets has became the main stream in consumer lives. Hwaling practices his specialty with long-term experience in this memory field to drive quality products and services to customers.

DDR3 / DDR3 SDRAM Supplier in Taiwan

Axeme - Hwaling Technology Co., Ltd. is proud to offer all of the leading brands in performance DDR3 / DDR3 SDRAM, at prices suitable for any budget. Most importantly, we back every one of our products with the best one-on-one customer service you'll find anywhere. For over number years, we've offered the trusted DDR3 / DDR3 SDRAM to fit our customers requirement. Thank you for your time and business, if you have any questions or needs, please do not hesitate to contact us.
Item No. Product Name Density Organization Voltage Package Remark File Download
H2A401G1666A DDR3 SDRAM 1Gb 64Mb x 16 1.5V FBGA-96 9x13mm H2A401G1666A _DDR3_64Mx16(1.4 MB)
H2A401G1666B DDR3 SDRAM 1Gb 64Mb x 16 1.5V FBGA-96 9x13mm H2A401G1666B _DDR3_64Mx16 (967 KB)
H2A401G0866B DDR3 SDRAM 1Gb 128Mb x 8 1.5V FBGA-78 8x10.5mm H2A401G0866B _DDR3_128Mx8(1.6 MB)
H2A402G1666A DDR3 SDRAM 2Gb 128Mb x 16 1.5V FBGA-96 8x13mm H2A402G1666A_DDR3_128Mx16(8x13mm) (1008 KB)
9x13mm H2A402G1666A_DDR3_128Mx16(1.2 MB)
H2A402G1666B DDR3 SDRAM 2Gb 128Mb x 16 1.5V FBGA-96 7.5x13mm H2A402G1666B_DDR3_128Mx16(7.5x13mm) (1.8 MB)
9x13mm H2A402G1666B_DDR3_128Mx16 (999 KB)
H2A402G1686B DDR3 SDRAM 2Gb 128Mb x 16 1.35V FBGA-96 9x13mm H2A402G1686B_DDR3_128Mx16(1.3 MB)
H2A402G1666C DDR3 SDRAM 2Gb 128Mb x 16 1.5V FBGA-96 8x14mm H2A402G1666C_DDR3_128Mx16 (1005 KB)
H2A402G0866B DDR3 SDRAM 2Gb 256Mb x 8 1.5V FBGA-78 8x10.5mm H2A402G0866B_DDR3_256Mx8(1.3 MB)
H2A402G0866C DDR3 SDRAM 2Gb 256Mb x 8 1.5V FBGA-78 8x10.5mm H2A402G0866C_DDR3_256Mx8(1.3 MB)
H2A404G1666A DDR3 SDRAM 4Gb 256Mb x 16 1.5V FBGA-96 8x13mm H2A404G1666A _DDR3_256Mx16 (824 KB)
H2A404G1666C DDR3 SDRAM 4Gb 256Mb x 16 1.5V FBGA-96 7.5x13.5mm H2A404G1666C_DDR3_256Mx16(7.5x13.5mm) (839 KB)
8x14mm H2A404G1666C_DDR3_256Mx16(8x14mm) (853 KB)
H2A404G1666J DDR3 SDRAM 4Gb 256Mb x 16 1.5V FBGA-96 7.5x13mm H2A404G1666J_DDR3_256Mx16 (836 KB)
H2A404G0866A DDR3 SDRAM 4Gb 512Mb x 8 1.5V FBGA-78 9x10.5mm H2A404G0866A_DDR3_512Mx8 (1.1 MB)
H2A404G0866C DDR3 SDRAM 4Gb 512Mb x 8 1.5V FBGA-78 9x10.5mm H2A404G0866C_DDR3_512Mx8(1.3 MB)
H2A408G3266A DDR3 SDRAM 8Gb 256Mb x 32 1.5V FBGA-136 DDP 12x14mm H2A408G3266A _DDR3_256Mx32(1.7 MB)
H2A408G3286A DDR3 SDRAM 8Gb 256Mb x 32 1.35V FBGA-136 DDP 12x14mm H2A408G3286A _DDR3_256Mx32(1.5 MB)
H2A408G1666A DDR3 SDRAM 8Gb 512Mb x 16 1.5V FBGA-96 DDP 10x13mm working(32 KB)

H2A401G1666A

1Gb (8Mx8Banksx16) DDR3 SDRAM

The H2A401G1666A is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1G bits which organized as 8Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ. Available package: FBGA-96Ball (with 0.8mm - 0.8mm ball pitch)

H2A401G1666B

1Gb (8Mx8Banksx16) DDR3 SDRAM

The H2A401G1666B is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1G bits which organized as 8Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ. Available package: WBGA-96Ball (with 0.8mm - 0.8mm ball pitch)

H2A401G0866B

1Gb (16M×8Bank×8) DDR 3 SDRAM

The H2A401G0866B is a 1G bits DDR3 SDRAM, organized as 16,777,216 words × 8 banks × 8 bits. This device achieves high speed transfer rates up to 1600 Mb/sec/pin (DDR3-1600) for various applications.
The H2A401G0866B is designed to comply with the following key DDR3 SDRAM features such as posted /CAS, programmable /CAS Write Latency (CWL), ZQ calibration, on die termination and asynchronous reset. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous fashion.

H2A402G1666A

2Gb (16Mx8Banksx16) DDR3 SDRAM

The H2A402G1666A is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
  • posted CAS with additive latency,
  • write latency = read latency -1,
  • On Die Termination,
  • programmable driver strength data,
  • seamless BL4 access with bank-grouping.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
Available package: FBGA-96Ball (with 0.8mm x 0.8mm ball pitch)

H2A402G1666B

2Gb (16Mx8Banksx16) DDR3 SDRAM

The H2A402G1666B is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination,
  4. programmable driver strength data,
  5. seamless BL4 access with bank-grouping.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
Available package: FBGA-96Ball (with 0.8mm x 0.8mm ball pitch)

H2A402G1686B

2Gb (16Mx8Banksx16) DDR3 SDRAM

The H2A402G1686B is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination,
  4. programmable driver strength data,
  5. seamless BL4 access with bank-grouping.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.35V(1.283V to 1.45V) VDD and VDDQ.
Available package: FBGA-96Ball (with 0.8mm x 0.8mm ball pitch)

H2A402G1666C

2Gb (16Mx8Banksx16) DDR3 SDRAM

The H2A402G1666C is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed
double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination,
  4. programmable driver strength data,
  5. seamless BL4 access with bank-grouping.

All of the control and address inputs
are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in
a /RAS and /CAS multiplexing style.
The 2Gb DDR3 devices operates with a single power supply:1.5V±0.075V VDD and VDDQ.

H2A402G0866B

2Gb (32Mx8Banksx8) DDR3 SDRAM

The H2A402G0866B is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 32Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination,
  4. programmable driver strength data,
  5. seamless BL4 access with bank-grouping.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)

H2A402G0866C

2Gb (32Mx8Banksx8) DDR3 SDRAM

The H2A402G0866C is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 32Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination,
  4. programmable driver strength data,
  5. seamless BL4 access with bank-grouping.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)

H2A404G1666A

4Gb (32Mx8Banksx16) DDR3 SDRAM

The H2A404G1666A is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed
double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.

H2A404G1666C

4Gb (32Mx8Banksx16) DDR3 SDRAM

The H2A404G1666C is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed
double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.

H2A404G1666J

4Gb (32Mx8Banksx16) DDR3 SDRAM

The H2A404G1666J is a high speed Double Date Rate 3 (DDR3) Synchronous DRAM fabricated with ultra high performance CMOS process containing 4G bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed
double-data-rate transfer rates of up to 1866 Mb/sec/pin (DDR3-1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.

H2A404G0866A

4Gb (64Mx8Banks×8) DDR3 SDRAM

The 4Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM Containing 4,294,967,296 bits.
It is internally configured as an octal-bank DRAM.
The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks.
These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

H2A404G0866C

4Gb (64Mx8Banks×8) DDR3 SDRAM

The H2A404G0866C is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 4,294,967,296 bits which organized as 64Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination,
  4. programmable driver strength data,
  5. seamless BL4 access with bank-grouping.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 4Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
Available package: FBGA-78Ball (with 0.8mm x 0.8mm ball pitch)

H2A408G3266A

8Gb (32Mx8Banks×32) DDR3 SDRAM

The H2A408G3266A is a high speed stack multi-chip package integrated 4Gbits x2 DDR3 SDRAM and fabricated with ultra high performance CMOS process containing 8G bits which organized as 32Mbits x 8 banks by 32 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.5V ± 0.075V VDD and VDDQ.

H2A408G3286A

8Gb (32Mx8Banks×32) DDR3 SDRAM

The H2A408G3286A is a high speed stack multi-chip package integrated 4Gbits x2 DDR3 SDRAM and fabricated with ultra high performance CMOS process containing 8G bits which organized as 32Mbits x 8 banks by 32 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
  1. posted CAS with additive latency,
  2. write latency = read latency -1,
  3. On Die Termination
  4. programmable driver strength data,
  5. seamless BL4 access.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 8Gb DDR3 devices operates with a single power supply: 1.35V ±1.35V -0.065/+0.1V or 1.5V ± 0.075V VDD and VDDQ.
With our advance research on day to day needs of consumer, our products are at the front. We are best in the manufacturing of DDR3 / DDR3 SDRAM. Our strict inspections and testing have ensured that all our DDR3 / DDR3 SDRAM achieve a high level of performance even in harsh conditions. We strive to provide the same level of service to our clients as our products enable our clients to provide. This means we will customize orders, negotiate fairly, and it means that we look forward to working with you!