DDR2 SDRAM Supplier in Taiwan
512Mb (8Mx4Banks×16) DDR2 SDRAM
The chip is designed to comply with the following key DDR2 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- On Die Termination.
All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O s are synchronized with a pair of bidirectional strobes (DQS, DQS) in a source synchronous fashion.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.