DDR2 SDRAM Manufacturer in Taiwan
512Mb (8Mx4Banks×16) DDR2 SDRAM
The chip is designed to comply with the following key DDR2 SDRAM features:
- posted CAS with additive latency,
- write latency = read latency -1,
- Off-Chip Driver (OCD) impedance adjustment and On Die Termination
- normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 512 Mb DDR2 devices operate with a single power supply: 1.8V ± 0.1V VDD and VDDQ.