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DDR2 SDRAM Manufacturer
Axeme - Hwaling Technology Co., Ltd. is one of the world's leading premium brands for DRAM IC, DDR2 SDRAM. The family business is headquartered in Taiwan, stands for innovation, tradition and exceptional style. Axeme - Hwaling Technology Co., Ltd. is a well reputed organization dealing with the manufacturing and supplying of DRAM IC, DDR2 SDRAM and other relative accessories. Moreover, we have always been committed to reaching new heights in innovation, leadership and customer satisfaction.
H2A35120856B
1Gb (16Mx4Banksx8) DDR2 SDRAM
The H2A35120856B is a 512M bits DDR2 SDRAM, organized as 16,777,216 words x 4 banks x 8 bits.
This device achieves high speed transfer rates up to 800Mb/sec/pin (DDR2-800) for general applications. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CLK rising and /CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- /DQS pair in a source synchronous fashion.
This device achieves high speed transfer rates up to 800Mb/sec/pin (DDR2-800) for general applications. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CLK rising and /CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- /DQS pair in a source synchronous fashion.
Features :
- Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
- Double Data Rate architecture: two data transfers per clock cycle
- CAS Latency: 3, 4, 5 and 6
- Burst Length: 4 and 8
- Bi-directional, differential data strobes (DQS an/DQS ) are transmitted / received with data
- Edge-aligned with Read data and center-aligned with Write data
- DLL aligns DQ and DQS transitions with clock
- Differential clock inputs (CLK and /CLK )
- Data masks (DM) for write data
- Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS
- Posted /CAS programmable additive latency supported to make command and data bus efficiency
- Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
- Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
- Auto-precharge operation for read and write bursts
- Auto Refresh and Self Refresh modes
- Precharged Power Down and Active Power Down
- Write Data Mask
- Write Latency = Read Latency - 1 (WL = RL - 1)
- Interface: SSTL_18
- Packaged in WBGA 60 Ball (8X12.5 mm2 ), using Lead free materials with RoHS compliant
Also, we are have an expert team of engineers both in the Taiwan and overseas and a world-class supply chain ensuring prompt delivery of quality products. Our DRAM IC, DDR2 SDRAM is of supreme quality and are much appreciated by the customers for their high-tech designs, user-friendliness and operational efficiency.
For over 10 years, we've offered the trusted DRAM IC, DDR2 SDRAM to fit our customers requirement. Let us assist with your requirement and question of DRAM IC, DDR2 SDRAM.
For over 10 years, we've offered the trusted DRAM IC, DDR2 SDRAM to fit our customers requirement. Let us assist with your requirement and question of DRAM IC, DDR2 SDRAM.