SDRAM Supplier
H2A11281636B
128Mb (2M×4Bank×16) Synchronous DRAM
The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL.
Packaged in TFBGA 54 Ball (8x8 mm^2).
- All Inputs are Sampled at the Rising Edge of the System Clock
- Auto Refresh and Self Refresh
- 4,096 Refresh Cycles / 64ms (15.625us)
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)